Semiconductor memories such as a DRAM store data in memory cells. The memory cell includes an access transistor and a capacitor. The capacitor is coupled to one of paired bit lines via the access transistor. During writing of data, one of the bit lines is controlled to a high level (power supply voltage) while the other bit line is controlled to a low level (ground voltage). In this state, the access transistor is turned on and thus the memory cell holds a charge in the capacitor to store a logical value corresponding to the high level or the low level. During standby, a pair of bit lines is precharged to a reference voltage Vref. When data is read, a select transistor is turned on. The voltage of one of the bit lines slightly changes from the reference voltage Vref according to the charge held in the capacitor, resulting in a voltage difference between the paired bit lines. The generated voltage difference is amplified by a sense amplifier circuit and is read as output data by an external circuit.
In this case, ½ VDD (hereinafter, will be called HVDD) that is an intermediate voltage between a ground voltage GND and a power supply voltage VDD is generally used as the reference voltage Vref.
Improved cell holding characteristics are desirable for a semiconductor memory. It is known that the reference voltage Vref is set at a voltage lower than HVDD to improve the cell holding characteristics. Generally, an NMOS transistor acting as a switch circuit is provided between a memory cell and a pair of bit lines. In the case where high-level data is stored in the memory cell, the charge of the memory cell leaks to the back bias of the NMOS transistor, which may lose the charge of the memory cell. Consequently, the voltage of the bit line does not sufficiently increase during reading, so that a voltage difference between the paired bit lines is hardly amplified. In this case, the reference voltage Vref set at a low voltage leads to an increase in voltage difference between the reference voltage Vref and the voltage of the bit line. Thus, a reading margin can be increased.
In this respect, Japanese Unexamined Patent Publication No. 2010-73299 discloses a technique of improving data holding characteristics while preventing a reduction in the speed of a semiconductor device. A semiconductor memory described in Japanese Unexamined Patent Publication No. 2010-73299 will be described below.
FIG. 1 is a circuit diagram illustrating a semiconductor memory 100 described in Japanese Unexamined Patent Publication No. 2010-73299. The semiconductor memory 100 includes a reference voltage power supply circuit 102, a first memory circuit 101-1, and a second memory circuit 101-2. The reference voltage power supply circuit 102 supplies a reference voltage Vref to a reference voltage wiring 108.
The first memory circuit 101-1 includes pairs of bit lines (D11-DB11, D12-D812), sense amplifier circuits (103-1, 103-2), precharge circuits (104-1, 104-2), a pull-down circuit 105-1, and a plurality of memory cells (106-1, 106-2). The memory cell 106-1 is coupled to the bit line D11 via a switch circuit while the memory cell 106-2 is coupled to the bit line D12 via a switch circuit. These switch circuits are turned on when a word line WL0 is selected. The sense amplifier circuit 103-1 amplifies a voltage difference between the paired bit lines (D11-DB11) when a control signal SEC) is turned on. The sense amplifier circuit 103-2 amplifies a voltage difference between the paired bit lines (D12-DB12) when the control signal SE0 is turned on. The precharge circuit 104-1 couples the pair of bit lines (D11-DB11) to the reference voltage wiring 108 when a control signal PDL0G is turned on. The precharge circuit 104-2 couples the pair of bit lines (D12-DB12) to the reference voltage wiring 108 when a control signal PDL0 is turned on. The pull-down circuit 105-1 pulls down the pair of bit lines (D11-DB11) to a ground voltage GND when a control signal PGL0 is turned on. Moreover, a parasitic capacitance 107 occurs between the paired bit lines (D11-DB11, D12-DB12).
The second memory circuit 101-2 is identical in configuration to the first memory circuit 101-1. Specifically, the second memory circuit 101-2 includes pairs of bit lines (D22-DB22, D21-DB21), sense amplifier circuits (103-3, 103-4), precharge circuits (104-3, 104-4), a pull-down circuit 105-2, and a plurality of memory cells (106-3, 106-4). When a word line WL1 is selected, the memory cells 106 (106-3, 106-4) are coupled to the respective bit lines (D22, D21). The sense amplifier circuits (103-3, 103-4) are controlled by a control signal SEl. The precharge circuits (104-3, 104-4) are controlled by control signals (PDL1G, PDL1). The pull-down circuit 105-2 is controlled by a control signal PGL1.
A method of operating the semiconductor memory 100 will be described below. When the first memory circuit 101-1 is selected in the semiconductor memory 100, the second memory circuit 101-2 is controlled to an unselected state and is operated as a dummy memory circuit. Referring to FIGS. 2 and 3, a data reading operation in the first memory circuit 101-1 will be described below. FIGS. 2 and 3 are timing charts showing the method of operating the semiconductor memory 100. FIG. 2 shows the waveforms of the signals. FIG. 3 shows the voltages of the bit lines (D11, D12, D21, D22, DB11, DB12, DB21, DB22).
As shown in FIG. 2, in a standby period before reading (before time t1), the control signals (PDL0, PDL0G, PDL1, PDL1G) are high-level signals. Thus, the precharge circuits 104 (104-1 to 104-4) are turned on in the memory circuits (101-1, 101-2). In other words, all the bit lines (D11, D12, D21, D22, DB11, DB12, DB21, DB22) are coupled to the reference voltage wiring 108. This allows precharging of the bit lines to the reference voltage Vref (FIG. 3).
As shown in FIG. 2, the control signals (PDL0, PDL0G, PDL1G) are switched to a low level at time t1 during reading. Thus, the precharging of the paired bit lines (D11-DB11, D12-DB12, D22-DB22) is reset.
At time t2, the word line WL0 is turned on. Specifically, the word line WL0 in the first memory circuit 101-1 is selected. In the first memory circuit 101-1, the memory cells (106-1 and 106-2) are coupled to the respective bit lines (D11, D12). It is assumed that high-level data is stored in the memory cells 106-1 and 106-2. In this case, as shown in FIG. 3, the voltages of the bit lines (D11, D12) slightly rise from the reference voltage Vref. As shown in FIG. 2, at time t2, the control signal PGL1 is switched to a high level. Thus, in the second memory circuit 101-2, the pull-down circuit 105-2 is operated to pull down the pair of bit lines D22 and DB22 to the ground voltage GND.
At time t3, the control signal SE0 is controlled to a high level. Thus, in the first memory circuit 101-1, the sense amplifier circuits 103-1 and 103-2 are operated to amplify a voltage difference between the paired bit lines (011-D811, D12-0312). Specifically, as shown in FIG. 3, the voltages of the bit lines D11 and D12 are raised to a power supply voltage VDD while the voltages of the bit lines DB11 and DB12 are reduced to the ground voltage GND. In this state, the amplified voltage difference is read as output data to an external circuit (not shown).
After the completion of reading, as shown in FIG. 2, the word line WL0 is turned off and the control signals SE0 and PGL1 are changed to a low level at time t4. At time t5, the control signals PDL0, PDL0G, and PDL1G are turned on. Thus, the pairs of bit lines (D11-DB11, D12-DB12, D22-DB22, D21-DB21) are all electrically coupled via the reference voltage wiring 108. This allows charge sharing among the pairs of bit lines. Before the charge sharing, the voltages of the bit lines D11 and D12 are equal to the power supply voltage VDD while the voltages of the bit lines (DB11, DB12, D22, DB22) are equal to the ground voltage CND. Thus, as a result of the charge sharing, as shown in FIG. 3, the voltages of the bit lines are averaged into ⅓ VDD (reference voltage Vref). The reference voltage power supply circuit 102 generates ⅓ VDD as the reference voltage Vref. In other words, the voltages of the bit lines D21 and DB21 are equal to the reference voltage Vref that does not affect the charge sharing. The reference voltage Vref, which is a voltage obtained after the charge sharing, can be controlled by changing the number of bit lines coupled to the reference voltage wirings 108 during the charge sharing.
In the semiconductor memory 100, the reference voltage Vref can be set at a voltage lower than ½ VDD. When the first memory circuit 100-1 is selected, the second memory circuit 100-2 is set to be unselected. Thus, in a reading period of the first memory circuit 100-1, the voltage of the pair of bit lines (D22-DB22) in the second memory circuit 100-2 can be pulled down. The pull-down may be called a setup for charge sharing. A setup can be performed during reading of data in the first memory circuit 100-1, enabling a high-speed circuit operation.